Abstract
The Ultra-Thin Body and Buried oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to Design/Technology Co-Optimization.
Keywords
strain ; stress ; FDSOI ; SiGe ; Local Layout-Effects ; Design/Technology Co-optimization
Jury members
- M. Sorin Cristoloveanu (IMEP LaHC) – Rapporteur
- M. Olivier Thomas (IM2NP) – Rapporteur
- Mme. Chantal Fontaine (LAAS) – Examinatrice
- M. Damien Querlioz (C2N) – Examinateur
- M. Alain Claverie (CEMES) – Directeur de thèse
- M. François ANDRIEU (CEA-LETI) – Encadrant
- M. Didier Dutartre (STMicroelectronics) – Encadrant