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Strain relaxation of SGOI fabricated by the Ge condensation technique

Warning ! Slippery interface

par PREVOTS Evelyne, PREVOTS Evelyne - publié le , mis à jour le

Studying in detail the impact of the fabrication steps of the n and p-MOS transistors on the crystalline deformations affecting the conduction channels of these transistors (Si for n-MOS, SiGe for p-MOS), CEMES researchers, in collaboration with Léti / CEA and STMicroelectronics, have demonstrated an unexpected stress relaxation mechanism in the SIGe-on-insulator structures, following the fabrication of SiGe by the so-called Ge condensation technique.

JPEG - 30.1 ko
Cartes de déformations et de rotation dans le plan d’une couche de SiGe sur isolant, en bord de tranchée STI ; (a) et (e), mesurées par DFEH ; (b) et (f), simulées par FEM « interface classique » et (c) et (g) simulées en introduisant une interface mince et élastique.

In the "FD-SOI Transistors" technology developed in particular by STMicroelectronics, the base wafer is formed of a thin layer of Si (10 nm) resting on top of an insulating silicon oxide layer. One of the difficulties to be overcome concerns the local transformation of Si into SiGe, required for the manufacture of high performance p-MOS in the vicinity of the Si-based n-MOS transistors. To do this, the technique called "Ge condensation" is used. It allows the gradual enrichment in Ge of a Si layer covered with an epitaxial SiGe layer during oxidation. During diffusion, the Ge atoms substitute from the Si atoms while keeping the "skeleton" of the silicon lattice in plane. The SiGe layer is then in compression in this plane, which increases the hole mobility.

Measurements made on CMOS devices at the 24 nm node have demonstrated that the expected performances for the p-MOS on SiGe were not found, especially when the actives on which these transistors were manufactured were small. In this context, CEMES and STMicroelectronics undertook to study the mechanical behavior of these layers during the manufacturing steps of p-MOS.
We therefore studied the evolution of the initial deformation in compression of the SiGe film during the fabrication of p-MOS transistors. For this, we compared the deformation maps of SiGe obtained by dark field electron holography with the results of numerical models describing the mechanics of the structure. In particular, we have shown unexpected behavior when the upper semiconductor is etched to fabricate the isolation trenches (STI) separating the Si n-MOS from the SiGe p-MOS. We note a dramatic and long-range relaxation of the SiGe layer initially in compression, without formation of extended defects. This phenomenon generates significant relative horizontal displacements between the SiGe layer and the underlying buried oxide (BOX). We suggest that the Ge-enrichment of the SiGe layer by the "Ge condensation" technique modifies the SiGe / BOX interface and that the observed stress relaxation results from the formation and propagation of interfacial defects from the edge to the center of the structure, in response to the high shear stress present at the interface.

These results not only make it possible to explain the electrical characteristics obtained on real devices but more importantly to propose alternative strategies (design) to keep the SiGe channels under compression and thus significantly improve the hole mobility in these devices.





  • Strain evolution of SiGe-on-insulator obtained by the Ge-condensation technique,
    Victor Boureau, Shay Reboh, Daniel Benoit, Martin Hÿtch and Alain Claverie
    APL Mater. 7 (2019) ; doi:10.1063/1.5088441
  • Impact of Some Processing Steps onto the Strain Distributions in FD-SOI CMOS Planar Devices : A Contribution of Dark-Field Electron Holography
    V. Boureau, D. Benoit and A. Claverie
    ECS Journal of Solid State Science and Technology, 7 (9) P473-P479 (2018)




Dr. Daniel BENOIT (ST)